Field of the Invention
The invention relates to an integrated circuit, and more particularly to a standard cell of an integrated circuit.
Description of the Related Art
In semiconductor design, standard cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. A standard cell is formed by a plurality of transistor and interconnect structures that provide a Boolean logic function (e.g. AND, OR, XOR, XNOR, inverters) or a storage function (e.g. flip-flop or latch). The standard cells are realized as fixed-height, variable-width full-custom cells. The standard cells are arranged in rows in a semiconductor substrate. In between the rows are routing areas for interconnecting the standard cells. Furthermore, power leafs may also be arranged through the routing areas or may have designed areas overlying the standard cells.
In order to simplify the ASIC design process, various vendors have developed various standard cell libraries. Use of the standard cells is advantageous to save time and cost for designing various ASICs. Furthermore, the standard cells are typically optimized full-custom layouts, which minimize delays and area.